1. Field
The present invention relates to a printed circuit board and a fabrication method thereof, which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern.
2. Description of the Related Art
As semiconductor chip manufacturing technology has advanced, the development of technology for the fabrication of package boards on which semiconductor chips are mounted has been actively conducted.
Specifically, after the middle of the 1990s, ball grid arrays (BGAs), which adopt a wire bonding process to connect ICs with boards, were commonly used. However, due to an increase in the number of I/O pins of semiconductor ICs, these methods have a limitation in that it is impossible to mount high-speed, high-performance ICs having small sizes.
Thus, technology of using flip chip interconnects to electrically connect ICs with boards was recently developed. Package products mounted on boards using the flip chip interconnect technology are collectively called “FCIP” (Flip Chip in Package).
It is known that, in the case of substrates for such FCIP, the formation of high-density multilayer circuits having a circuit line width of less than 35 μm/35 μm is required. Methods for forming such HDI (high-density interconnection) may include laser build-up welding.
In this method, BT, FR-4 or other resins are impregnated into woven glass fabric to make a core. On both sides of such a core, a copper foil is laminated to a thickness of 18-35 μm to form an inner layer circuit, and then a subtractive process or a semi-additive process is performed to fabricate a printed circuit board.
The method for forming build-up patterns on a board having an inner layer circuit pattern formed thereon is shown in FIGS. 1A to 1F.
FIGS. 1A to 1F are process cross-sectional views illustrating the prior method for fabricating a printed circuit board.
As shown in FIG. 1A, an inner layer circuit pattern 12 is first formed on both sides of a core 10 using a general process.
In this respect, the core 10 is made of a copper-clad laminate (CCL), and as the insulating material of CCL, FR-4 or epoxy resin, impregnated into woven glass fabric, is mainly used.
After the inner layer circuit pattern 12 is formed, as shown in FIG. 1B, an ink-type thermosetting resin 14 is applied on the core board having the inner layer circuit pattern 12 formed thereon, or a dry film-type resin is attached to the core board. Then, the applied or attached resin is cured.
Then, as shown in FIG. 1C, a given location of the board structure is irradiated with a laser beam to form a via-hole 18.
After the via-hole 18 is formed, as shown in FIG. 1D, the surface of the board having the via-hole 18 formed therein is roughened and subjected to CZ treatment. Then, a copper seed layer 20 is formed on the surface of the board using an electroless copper plating process. In this respect, the copper seed layer 20 is formed after a Ni—Cr tie-layer (not shown) is formed.
After the copper seed layer 20 is formed, a dry film 22 is attached on the copper seed layer 20, and then, as shown in FIG. 1E, the portion where a circuit pattern is to be formed is exposed through a conventional photo-etching process comprising exposure and development.
Then, a conductive layer 24 is formed using a copper electroplating process, followed by removal of the dry film 22. After the dry film 22 is removed, the portion of the copper seed layer 20 on which the conductive layer 24 was not formed is removed using a flash etching process, thus forming an outer layer circuit pattern 26 as shown in FIG. 1F.
After the outer layer circuit pattern 26 is formed, in order to form a multi-layer printed circuit board, an adhesive layer and an insulating layer are sequentially formed on the outer layer circuit pattern 26 and are pressed with a press.
Then, after the outermost layer circuit pattern is formed in the outermost layer, the outermost layer circuit pattern, which is connected to an external terminal, is exposed through a solder resist opening process, and a gold plating layer is formed on the exposed outermost layer circuit pattern.
However, this prior printed circuit board has problems in that, because FR-4 or epoxy-based insulating material having a high dielectric constant (higher than 4.5), a high loss coefficient (higher than 0.05), and a high propagation delay time (higher than 180 ps/in), is used, not only is a large amount of heat generated, but also the electrical properties are reduced, due to the reduction of signal transmission speed and the loss of the transmitted signal. Also, there is a problem in that, because CCL having resin impregnated into woven glass fabric is used in the core, the thickness of the package is increased.
Moreover, the method of fabricating the printed circuit board using sputter Flexible Copper Clad Laminate (FCCL) according to the prior art has a problem in that, because the copper seed layer is formed after the formation of the Ni—Cr tie-layer, a process of depositing the tie-layer and a process of etching the tie-layer are required, and thus a long processing time is needed.
Furthermore, the method for fabricating the printed circuit board according to the prior art has problems in that, because the insulating layer is deposited on the inner layer circuit pattern 12 using an epoxy or acryl-based adhesive layer in order to fabricate a multilayer printed circuit board, not only are a process time and process cost for forming the adhesive layer increased, but also the excellent electrical properties of the insulating layer are reduced due to the adhesive layer, and the thickness of the chip package is increased.
In addition, the method for fabricating the printed circuit board according to the prior art has a problem in that a large amount of waste, such as wastewater and contaminants, are generated in the pretreatment process, such as CZ treatment or desmearing treatment, and the wet process such as electroless copper plating for forming the copper seed layer, thus causing environmental contamination.